Use VecDeque instead of Vec in sigverify stage (#22538) (#22550)

avoid bad performance of remove(0) for a single sender

(cherry picked from commit 49443406fd)

# Conflicts:
#	core/src/sigverify_stage.rs

Co-authored-by: sakridge <sakridge@gmail.com>
This commit is contained in:
mergify[bot]
2022-01-19 01:46:34 +00:00
committed by GitHub
parent 2546ef4ad6
commit 2b87d99479
2 changed files with 18 additions and 8 deletions

View File

@ -13,7 +13,7 @@ use {
solana_sdk::timing,
solana_streamer::streamer::{self, PacketBatchReceiver, StreamerError},
std::{
collections::HashMap,
collections::{HashMap, VecDeque},
sync::mpsc::{Receiver, RecvTimeoutError},
thread::{self, Builder, JoinHandle},
time::Instant,
@ -145,17 +145,17 @@ impl SigVerifyStage {
for (packet_index, packets) in batch.packets.iter().enumerate() {
let e = received_ips
.entry(packets.meta.addr().ip())
.or_insert_with(Vec::new);
e.push((batch_index, packet_index));
.or_insert_with(VecDeque::new);
e.push_back((batch_index, packet_index));
}
}
let mut batch_len = 0;
while batch_len < max_packets {
for (_ip, indexes) in received_ips.iter_mut() {
if !indexes.is_empty() {
indexes.remove(0);
indexes.pop_front();
batch_len += 1;
if batch_len >= MAX_SIGVERIFY_BATCH {
if batch_len >= max_packets {
break;
}
}