<h1>Introduction<aclass="headerlink"href="#introduction"title="Permalink to this headline">¶</a></h1>
<divclass="section"id="motivations">
<h2>Motivations<aclass="headerlink"href="#motivations"title="Permalink to this headline">¶</a></h2>
<p>Over the past decade, Deep Neural Networks (DNNs) have emerged as an important class of Machine Learning (ML) models, capable of achieving state-of-the-art performance across many domains ranging from natural language processing <aclass="reference internal"href="#sutskever2014"id="id1"><span>[SUTSKEVER2014]</span></a> to computer vision <aclass="reference internal"href="#redmon2016"id="id2"><span>[REDMON2016]</span></a> to computational neuroscience <aclass="reference internal"href="#lee2017"id="id3"><span>[LEE2017]</span></a>. The strength of these models lies in their hierarchical structure, composed of a sequence of parametric (e.g., convolutional) and non-parametric (e.g., rectified linearity) <em>layers</em>. This pattern, though notoriously computationally expensive, also generates a large amount of highly parallelizable work particularly well suited for multi- and many- core processors.</p>
<p>As a consequence, Graphics Processing Units (GPUs) have become a cheap and accessible resource for exploring and/or deploying novel research ideas in the field. This trend has been accelerated by the release of several frameworks for General-Purpose GPU (GPGPU) computing, such as CUDA and OpenCL, which have made the development of high-performance programs easier. Yet, GPUs remain incredibly challenging to optimize for locality and parallelism, especially for computations that cannot be efficiently implemented using a combination of pre-existing optimized primitives. To make matters worse, GPU architectures are also rapidly evolving and specializing, as evidenced by the addition of tensor cores to NVIDIA (and more recently AMD) micro-architectures.</p>
<p>This tension between the computational opportunities offered by DNNs and the practical difficulty of GPU programming has created substantial academic and industrial interest for Domain-Specific Languages (DSLs) and compilers. Regrettably, these systems – whether they be based on polyhedral machinery (<em>e.g.</em>, Tiramisu <aclass="reference internal"href="../chapter-2/related-work.html#baghdadi2021"id="id4"><span>[BAGHDADI2021]</span></a>, Tensor Comprehensions <aclass="reference internal"href="../chapter-2/related-work.html#vasilache2018"id="id5"><span>[VASILACHE2018]</span></a>) or scheduling languages (<em>e.g.</em>, Halide <aclass="reference internal"href="#jrk2013"id="id6"><span>[JRK2013]</span></a>, TVM <aclass="reference internal"href="#chen2018"id="id7"><span>[CHEN2018]</span></a>) – remain less flexible and (for the same algorithm) markedly slower than the best handwritten compute kernels available in libraries like <aclass="reference external"href="https://docs.nvidia.com/cuda/cublas/index.html">cuBLAS</a>, <aclass="reference external"href="https://docs.nvidia.com/deeplearning/cudnn/api/index.html">cuDNN</a> or <aclass="reference external"href="https://docs.nvidia.com/deeplearning/tensorrt/developer-guide/index.html">TensorRT</a>.</p>
<p>The main premise of this project is the following: programming paradigms based on blocked algorithms <aclass="reference internal"href="#lam1991"id="id8"><span>[LAM1991]</span></a> can facilitate the construction of high-performance compute kernels for neural networks. We specifically revisit traditional “Single Program, Multiple Data” (SPMD <aclass="reference internal"href="#auguin1983"id="id9"><span>[AUGUIN1983]</span></a>) execution models for GPUs, and propose a variant in which programs – rather than threads – are blocked. For example, in the case of matrix multiplication, CUDA and Triton differ as follows:</p>
<p>A key benefit of this approach is that it leads to block-structured iteration spaces that offer programmers more flexibility than existing DSLs when implementing sparse operations, all while allowing compilers to aggressively optimize programs for data locality and parallelism.</p>
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<divclass="section"id="challenges">
<h2>Challenges<aclass="headerlink"href="#challenges"title="Permalink to this headline">¶</a></h2>
<p>The main challenge posed by our proposed paradigm is that of work scheduling, i.e., how the work done by each program instance should be partitioned for efficient execution on modern GPUs. To address this issue, the Triton compiler makes heavy use of <em>block-level data-flow analysis</em>, a technique for scheduling iteration blocks statically based on the control- and data-flow structure of the target program. The resulting system actually works surprisingly well: our compiler manages to apply a broad range of interesting optimization automatically (e.g., automatic coalescing, thread swizzling, pre-fetching, automatic vectorization, tensor core-aware instruction selection, shared memory allocation/synchronization, asynchronous copy scheduling). Of course doing all this is not trivial; one of the purposes of this guide is to give you a sense of how it works.</p>
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<divclass="section"id="references">
<h2>References<aclass="headerlink"href="#references"title="Permalink to this headline">¶</a></h2>
<li><p>Ragan-Kelley et al., “Halide: A Language and Compiler for Optimizing Parallelism, Locality, and Recomputation in Image Processing Pipelines”, PLDI 2013</p></li>
