[GENERAL] Merged v1.0alpha into master. Added features are:

- A100 support via mma.16816
- Thread swizzling for conflict-free shared memory accesses without
padding
- Complete overhaul of the LLVM code generation in
codegen/selection/generator.cc to remove overengineering
- Added debugging capabilities in the Python binding
- Compilation error for kernels that spill

lib/codegen/transform/cts.cc

@@ -28,12 +28,14 @@ inline bool is_shmem_res(ir::value* v){
     return true;
   if(i->get_id() == ir::INST_COPY_TO_SHARED)
     return true;
+  if(i->get_id() == ir::INST_MASKED_LOAD_ASYNC)
+    return true;
   return false;
 }
 
 
 // run pass on module
-void add_copy(ir::instruction *parent, ir::value *x, ir::builder &builder, bool to_shared) {
+void cts::add_copy(ir::instruction *parent, ir::value *x, ir::builder &builder, bool to_shared) {
   auto *i = dynamic_cast<ir::instruction*>(x);
   // not an instruction
   if(!i) {
@@ -58,8 +60,9 @@ void add_copy(ir::instruction *parent, ir::value *x, ir::builder &builder, bool
   // copy
   builder.set_insert_point_after(i);
   ir::value *copy;
-  if(to_shared)
+  if(to_shared){
     copy = builder.create_copy_to_shared(x);
+  }
   else
     copy = builder.create_copy_from_shared(x);
   parent->replace_uses_of_with(x, copy);