[Triton-MLIR][BACKEND] insert_slice_async on GPUs < sm80 (#908)
`insert_slice_async` is decomposed into `load + insert_slice` in the backend. Not sure if V100 perf can match the master branch though in this way. Maybe the performance can be improved if instructions are arranged in the following form: ``` %0 = load %1 = load %2 = load ... insert_slice %0 insert_slice %1 insert_slice %2 ``` Tested on A100 when manually enabling this decomposition. Tests on V100 haven't been integrated yet, we can divide the tests into two phases: 1. Test only load, insert_slice, and insert_slice_async, given TritonGPU IRs in `test_backend.py`. 2. End to end gemm tests on V100.
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@@ -12,6 +12,8 @@ bool isSharedEncoding(Value value);
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bool maybeSharedAllocationOp(Operation *op);
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bool maybeAliasOp(Operation *op);
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std::string getValueOperandName(Value value, AsmState &state);
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template <typename Int> Int product(llvm::ArrayRef<Int> arr) {
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@@ -43,6 +43,12 @@ def ConvertTritonGPUToLLVM : Pass<"convert-triton-gpu-to-llvm", "mlir::ModuleOp"
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"mlir::triton::gpu::TritonGPUDialect",
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"mlir::NVVM::NVVMDialect",
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"mlir::StandardOpsDialect"];
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let options = [
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Option<"computeCapability", "compute-capability",
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"int32_t", /*default*/"80",
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"device compute capability">
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];
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}
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#endif
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@@ -33,7 +33,8 @@ struct NVVMMetadataField {
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static constexpr char Kernel[] = "nvvm.kernel";
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};
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std::unique_ptr<OperationPass<ModuleOp>> createConvertTritonGPUToLLVMPass();
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std::unique_ptr<OperationPass<ModuleOp>>
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createConvertTritonGPUToLLVMPass(int computeCapability = 80);
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} // namespace triton
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@@ -25,7 +25,8 @@ void addExternalLibs(mlir::ModuleOp &module,
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// Translate TritonGPU dialect to LLVMIR, return null if failed.
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std::unique_ptr<llvm::Module>
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translateTritonGPUToLLVMIR(llvm::LLVMContext *llvmContext,
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mlir::ModuleOp module);
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mlir::ModuleOp module,
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int computeCapability);
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// Translate mlir LLVM dialect to LLVMIR, return null if failed.
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std::unique_ptr<llvm::Module>
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