[Triton-MLIR] Two fixes on allocation and backend related with MMA v1 (#930)
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@@ -13,6 +13,7 @@
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using ::mlir::triton::gpu::BlockedEncodingAttr;
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using ::mlir::triton::gpu::DotOperandEncodingAttr;
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using ::mlir::triton::gpu::getContigPerThread;
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using ::mlir::triton::gpu::getOrder;
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using ::mlir::triton::gpu::getShapePerCTA;
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using ::mlir::triton::gpu::getSizePerThread;
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@@ -60,8 +61,8 @@ getScratchConfigForCvtLayout(triton::gpu::ConvertLayoutOp op, unsigned &inVec,
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assert(srcLayout && dstLayout &&
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"Unexpect layout in getScratchConfigForCvtLayout()");
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auto [inOrd, outOrd] = getCvtOrder(srcLayout, dstLayout);
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unsigned srcContigPerThread = getSizePerThread(srcLayout)[inOrd[0]];
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unsigned dstContigPerThread = getSizePerThread(dstLayout)[outOrd[0]];
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unsigned srcContigPerThread = getContigPerThread(srcLayout)[inOrd[0]];
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unsigned dstContigPerThread = getContigPerThread(dstLayout)[outOrd[0]];
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// TODO: Fix the legacy issue that ourOrd[0] == 0 always means
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// that we cannot do vectorization.
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inVec = outOrd[0] == 0 ? 1 : inOrd[0] == 0 ? 1 : srcContigPerThread;
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