rename sharded_layout => blocked_layout
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@@ -37,7 +37,7 @@ static LogicalResult parseIntArrayAttr(AsmParser &parser,
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#include "triton/Dialect/TritonGPU/IR/TritonGPUAttrDefs.cpp.inc"
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Attribute
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TritonGPUShardedEncodingAttr::parse(AsmParser &parser, Type type) {
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TritonGPUBlockedEncodingAttr::parse(AsmParser &parser, Type type) {
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if (parser.parseLess().failed())
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return {};
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// Parse the data as a dictionary
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@@ -94,14 +94,14 @@ TritonGPUShardedEncodingAttr::parse(AsmParser &parser, Type type) {
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}
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}
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return parser.getChecked<TritonGPUShardedEncodingAttr>(parser.getContext(),
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return parser.getChecked<TritonGPUBlockedEncodingAttr>(parser.getContext(),
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threadTileSize,
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warpTileSize,
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blockTileSize,
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order);
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}
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void TritonGPUShardedEncodingAttr::print(mlir::AsmPrinter &printer) const {
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void TritonGPUBlockedEncodingAttr::print(mlir::AsmPrinter &printer) const {
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printer << "<{"
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<< "threadTileSize = [" << getThreadTileSize() << "]"
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<< ", warpTileSize = [" << getWarpTileSize() << "]"
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@@ -46,7 +46,7 @@ TritonGPUTypeConverter::TritonGPUTypeConverter(MLIRContext *context,
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remainingThreads /= blockTileSize[dim];
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// TODO: will we need repetition?
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}
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Attribute encoding = triton::gpu::TritonGPUShardedEncodingAttr::get(
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Attribute encoding = triton::gpu::TritonGPUBlockedEncodingAttr::get(
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context, threadTileSize, warpTileSize, blockTileSize, order);
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return RankedTensorType::get(shape, elementType, encoding);
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});
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@@ -50,7 +50,7 @@ private:
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if (!encoding)
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return dotOp.emitError() << name << " should have encoding";
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if (!encoding.isa<triton::gpu::TritonGPUMmaEncodingAttr>() &&
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!encoding.isa<triton::gpu::TritonGPUShardedEncodingAttr>())
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!encoding.isa<triton::gpu::TritonGPUBlockedEncodingAttr>())
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return dotOp.emitError() << name << " should be of distributed layout";
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if (name == 'c')
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cLayout = encoding;
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