more TritonGPU unit tests
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@@ -11,7 +11,10 @@ int main(int argc, char **argv) {
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mlir::DialectRegistry registry;
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registry.insert<mlir::triton::TritonDialect,
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mlir::triton::gpu::TritonGPUDialect>();
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mlir::triton::gpu::TritonGPUDialect,
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mlir::arith::ArithmeticDialect,
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mlir::StandardOpsDialect,
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mlir::scf::SCFDialect>();
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return mlir::asMainReturnCode(
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mlir::MlirOptMain(argc, argv, "Triton (GPU) optimizer driver\n", registry)
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@@ -102,12 +102,12 @@ TritonGPUShardedEncodingAttr::parse(AsmParser &parser, Type type) {
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}
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void TritonGPUShardedEncodingAttr::print(mlir::AsmPrinter &printer) const {
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printer << "<"
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printer << "<{"
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<< "threadTileSize = [" << getThreadTileSize() << "]"
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<< ", warpTileSize = [" << getWarpTileSize() << "]"
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<< ", blockTileSize = [" << getBlockTileSize() << "]"
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<< ", order = [" << getOrder() << "]"
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<< ">";
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<< "}>";
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}
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Attribute
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@@ -175,11 +175,11 @@ TritonGPUSharedEncodingAttr::parse(AsmParser &parser, Type type) {
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}
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void TritonGPUSharedEncodingAttr::print(AsmPrinter &printer) const {
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printer << "<"
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printer << "<{"
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<< "vec = " << getVec()
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<< ", perPhase = " << getPerPhase()
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<< ", order = [" << getOrder() << "]"
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<< ">";
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<< "}>";
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}
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void TritonGPUDialect::initialize() {
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26
test/TritonGPU/layout.mlir
Normal file
26
test/TritonGPU/layout.mlir
Normal file
@@ -0,0 +1,26 @@
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// RUN: triton-opt %s -split-input-file -verify-diagnostics
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#reg = #triton_gpu.sharded_layout<{
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threadTileSize = [1, 1],
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warpTileSize = [32, 1],
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blockTileSize = [64, 1],
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order = [0, 1]
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}>
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#reg2 = #triton_gpu.sharded_layout<{
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threadTileSize = [2, 1],
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warpTileSize = [64, 1],
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blockTileSize = [128, 1],
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order = [0, 1]
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}>
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func @add(%arg0: tensor<256xi32, #reg>, %arg1: tensor<256xi32, #reg>) {
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%0 = arith.addi %arg0, %arg1 : tensor<256xi32, #reg>
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return
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}
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func @add(%arg0: tensor<256xi32, #reg>, %arg1: tensor<256xi32, #reg>) { // expected-note {{prior use here}}
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// expected-error @+1 {{use of value '%arg0' expects different type than prior uses}}
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%0 = arith.addi %arg0, %arg1 : tensor<256xi32, #reg2>
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return
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}
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