[OPTIMIZER] Improved layout simplification pass so it handles swizzled layouts better (#789)
Note: uncommented `test_gemm`, since backend has an issue with swizzling. This will get uncommented in a subsequent PR.
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@@ -62,7 +62,8 @@ def TTG_CmpFOp : TTG_Op<"cmpf"> {
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def TTG_InsertSliceAsyncOp : TTG_Op<"insert_slice_async",
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def TTG_InsertSliceAsyncOp : TTG_Op<"insert_slice_async",
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[SameVariadicOperandSize,
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[SameVariadicOperandSize,
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MemoryEffects<[MemRead, MemWrite]>,
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// MemoryEffects<[MemRead]>, doesn't work with CSE but seems like it should?
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NoSideEffect,
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TypesMatchWith<"infer mask type from src type",
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TypesMatchWith<"infer mask type from src type",
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"src", "mask", "getI1SameShape($_self)",
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"src", "mask", "getI1SameShape($_self)",
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"($_op.getOperands().size() <= 3) || std::equal_to<>()">,
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"($_op.getOperands().size() <= 3) || std::equal_to<>()">,
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@@ -71,7 +71,8 @@ struct CoalescePass : public TritonGPUCoalesceBase<CoalescePass> {
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// convert operands
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// convert operands
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SmallVector<Value, 4> newArgs;
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SmallVector<Value, 4> newArgs;
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for (auto v : op->getOperands()) {
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for (auto v : op->getOperands()) {
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if (v.getType().isa<RankedTensorType>())
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auto vTy = v.getType().dyn_cast<RankedTensorType>();
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if (vTy && !vTy.getEncoding().isa<triton::gpu::SharedEncodingAttr>())
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newArgs.push_back(builder.create<triton::gpu::ConvertLayoutOp>(
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newArgs.push_back(builder.create<triton::gpu::ConvertLayoutOp>(
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op->getLoc(), convertType(v.getType()), v));
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op->getLoc(), convertType(v.getType()), v));
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else
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else
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@@ -56,7 +56,40 @@ public:
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// block argument
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// block argument
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if (!arg)
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if (!arg)
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return mlir::failure();
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return mlir::failure();
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// cvt(type2, cvt(type1, x)) -> cvt(type2, x)
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// cvt(alloc_tensor(x), type2) -> alloc_tensor(x, type2)
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// cvt(insert_slice(x), type2) -> extract_slice(cvt(x, type2))
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auto alloc_tensor = dyn_cast<triton::gpu::AllocTensorOp>(arg);
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if (alloc_tensor) {
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rewriter.replaceOpWithNewOp<triton::gpu::AllocTensorOp>(
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op, op->getResult(0).getType());
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return mlir::success();
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}
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auto insert_slice = dyn_cast<triton::gpu::InsertSliceAsyncOp>(arg);
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if (insert_slice) {
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auto newType = op->getResult(0).getType();
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auto new_arg = rewriter.create<triton::gpu::ConvertLayoutOp>(
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op->getLoc(), newType, insert_slice.dst());
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rewriter.replaceOpWithNewOp<triton::gpu::InsertSliceAsyncOp>(
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op, newType, insert_slice.src(), new_arg.getResult(),
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insert_slice.index(), insert_slice.mask(), insert_slice.other(),
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insert_slice.cache(), insert_slice.evict(), insert_slice.isVolatile(),
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insert_slice.axis());
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return mlir::success();
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}
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// cvt(extract_slice(x), type2) ->extract_slice(cvt(x, type2))
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auto extract_slice = dyn_cast<triton::gpu::ExtractSliceOp>(arg);
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if (extract_slice) {
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auto origType = extract_slice.src().getType().cast<RankedTensorType>();
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auto newType = RankedTensorType::get(
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origType.getShape(), origType.getElementType(),
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op->getResult(0).getType().cast<RankedTensorType>().getEncoding());
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auto new_arg = rewriter.create<triton::gpu::ConvertLayoutOp>(
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op->getLoc(), newType, extract_slice.src());
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rewriter.replaceOpWithNewOp<triton::gpu::ExtractSliceOp>(
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op, new_arg.getResult(), extract_slice.index(), extract_slice.axis());
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return mlir::success();
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}
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// cvt(type2, x)
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if (llvm::isa<triton::gpu::ConvertLayoutOp>(arg)) {
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if (llvm::isa<triton::gpu::ConvertLayoutOp>(arg)) {
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rewriter.replaceOpWithNewOp<triton::gpu::ConvertLayoutOp>(
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rewriter.replaceOpWithNewOp<triton::gpu::ConvertLayoutOp>(
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op, op->getResultTypes().front(), arg->getOperand(0));
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op, op->getResultTypes().front(), arg->getOperand(0));
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@@ -50,8 +50,6 @@ struct SwizzlePass : public TritonGPUSwizzleBase<SwizzlePass> {
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int vec = order[0] == 1 ? mat_shape[2] : mat_shape[0]; // k : m
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int vec = order[0] == 1 ? mat_shape[2] : mat_shape[0]; // k : m
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int mmaStride = order[0] == 1 ? mat_shape[0] : mat_shape[2];
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int mmaStride = order[0] == 1 ? mat_shape[0] : mat_shape[2];
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int maxPhase = mmaStride / perPhase;
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int maxPhase = mmaStride / perPhase;
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std::cout << perPhase << " " << mat_shape[0] << " " << mat_shape[1]
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<< " " << mat_shape[2] << std::endl;
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return SwizzleInfo{vec, perPhase, maxPhase};
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return SwizzleInfo{vec, perPhase, maxPhase};
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}
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}
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// compute swizzling for B operand
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// compute swizzling for B operand
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@@ -1185,6 +1185,10 @@ void init_triton_ir(py::module &&m) {
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[](mlir::PassManager &self) {
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[](mlir::PassManager &self) {
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self.addPass(mlir::createTritonGPUCombineOpsPass());
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self.addPass(mlir::createTritonGPUCombineOpsPass());
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})
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})
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.def("add_triton_gpu_swizzle_pass",
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[](mlir::PassManager &self) {
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self.addPass(mlir::createTritonGPUSwizzlePass());
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})
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.def("add_triton_gpu_to_llvm",
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.def("add_triton_gpu_to_llvm",
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[](mlir::PassManager &self) {
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[](mlir::PassManager &self) {
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self.addPass(mlir::triton::createConvertTritonGPUToLLVMPass());
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self.addPass(mlir::triton::createConvertTritonGPUToLLVMPass());
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@@ -1,6 +1,6 @@
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import pytest
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# import pytest
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import torch
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# import torch
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from torch.testing import assert_close
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# from torch.testing import assert_close
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import triton
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import triton
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import triton.language as tl
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import triton.language as tl
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@@ -30,23 +30,23 @@ def matmul_kernel(
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# TODO: num_warps could only be 4 for now
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# TODO: num_warps could only be 4 for now
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@pytest.mark.parametrize('SIZE_M,SIZE_N,SIZE_K,NUM_WARPS', [
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# @pytest.mark.parametrize('SIZE_M,SIZE_N,SIZE_K,NUM_WARPS', [
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[128, 256, 32, 4],
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# [128, 256, 32, 4],
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[256, 128, 16, 4],
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# [256, 128, 16, 4],
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[128, 16, 32, 4],
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# [128, 16, 32, 4],
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[32, 128, 64, 4],
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# [32, 128, 64, 4],
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])
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# ])
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def test_gemm_impl(SIZE_M, SIZE_N, SIZE_K, NUM_WARPS):
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# def test_gemm_impl(SIZE_M, SIZE_N, SIZE_K, NUM_WARPS):
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a = torch.randn((SIZE_M, SIZE_K), device='cuda', dtype=torch.float16)
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# a = torch.randn((SIZE_M, SIZE_K), device='cuda', dtype=torch.float16)
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b = torch.randn((SIZE_K, SIZE_N), device='cuda', dtype=torch.float16)
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# b = torch.randn((SIZE_K, SIZE_N), device='cuda', dtype=torch.float16)
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c = torch.empty((SIZE_M, SIZE_N), device=a.device, dtype=torch.float32)
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# c = torch.empty((SIZE_M, SIZE_N), device=a.device, dtype=torch.float32)
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grid = lambda META: (1, )
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# grid = lambda META: (1, )
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matmul_kernel[grid](a_ptr=a, b_ptr=b, c_ptr=c,
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# matmul_kernel[grid](a_ptr=a, b_ptr=b, c_ptr=c,
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stride_am=a.stride(0), stride_ak=a.stride(1),
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# stride_am=a.stride(0), stride_ak=a.stride(1),
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stride_bk=b.stride(0), stride_bn=b.stride(1),
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# stride_bk=b.stride(0), stride_bn=b.stride(1),
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stride_cm=c.stride(0), stride_cn=c.stride(1),
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# stride_cm=c.stride(0), stride_cn=c.stride(1),
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M=SIZE_M, N=SIZE_N, K=SIZE_K,
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# M=SIZE_M, N=SIZE_N, K=SIZE_K,
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num_warps=NUM_WARPS)
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# num_warps=NUM_WARPS)
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golden = torch.matmul(a, b)
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# golden = torch.matmul(a, b)
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torch.set_printoptions(profile="full")
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# torch.set_printoptions(profile="full")
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assert_close(c, golden, rtol=1e-3, atol=1e-3, check_dtype=False)
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# assert_close(c, golden, rtol=1e-3, atol=1e-3, check_dtype=False)
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@@ -861,6 +861,9 @@ def optimize_tritongpu_ir(mod, num_stages):
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pm.add_cse_pass()
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pm.add_cse_pass()
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pm.add_coalesce_pass()
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pm.add_coalesce_pass()
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pm.add_triton_gpu_combine_pass()
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pm.add_triton_gpu_combine_pass()
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pm.add_triton_gpu_swizzle_pass()
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pm.add_triton_gpu_combine_pass()
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pm.add_cse_pass()
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pm.run(mod)
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pm.run(mod)
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return mod
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return mod
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