[ir][instruction] added identifier for each instruction
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@@ -103,39 +103,9 @@ Value* nvidia_cu_target::get_block_id(Module *module, IRBuilder<>& builder, unsi
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Intrinsic::nvvm_read_ptx_sreg_ctaid_y,
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Intrinsic::nvvm_read_ptx_sreg_ctaid_z
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};
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// bool z_order = true;
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// if(z_order && ax < 2){
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// static std::array<Intrinsic::ID, 3> n_cta_ids = {
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// Intrinsic::nvvm_read_ptx_sreg_nctaid_x,
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// Intrinsic::nvvm_read_ptx_sreg_nctaid_y,
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// Intrinsic::nvvm_read_ptx_sreg_nctaid_z
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// };
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// Value* cta_id_0 = builder.CreateIntrinsic(cta_ids[0], {}, {});
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// Value* cta_id_1 = builder.CreateIntrinsic(cta_ids[1], {}, {});
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// Value* n_cta_id_0 = builder.CreateIntrinsic(n_cta_ids[0], {}, {});
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// Value* n_cta_id_1 = builder.CreateIntrinsic(n_cta_ids[1], {}, {});
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// // global block ID
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// Value* bid = builder.CreateAdd(cta_id_0, builder.CreateMul(cta_id_1, n_cta_id_0));
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// // helper for minimum
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// auto Min = [&](Value *x, Value *y){
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// return builder.CreateSelect(builder.CreateICmpSGE(x, y), y, x);
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// };
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// // super-tile size
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// Value* sts = Min(builder.getInt32(16), n_cta_id_1);
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// // number of CTAs per super-block
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// Value *nscta = builder.CreateMul(n_cta_id_0, sts);
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// Value *bid0 = builder.CreateURem(builder.CreateUDiv(bid, sts), n_cta_id_0);
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// Value *bid1 = builder.CreateAdd(builder.CreateMul(builder.CreateUDiv(bid, nscta), sts),builder.CreateURem(bid, sts));
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// if(ax == 0)
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// return bid0;
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// else
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// return bid1;
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// }
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// else{
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Value* get_cta_id = Intrinsic::getDeclaration(module, cta_ids[ax]);
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Value* cta_id = builder.CreateCall(get_cta_id, {});
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return cta_id;
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// }
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Value* get_cta_id = Intrinsic::getDeclaration(module, cta_ids[ax]);
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Value* cta_id = builder.CreateCall(get_cta_id, {});
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return cta_id;
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}
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Value* nvidia_cu_target::get_local_id(Module *module, IRBuilder<>& builder, unsigned ax) {
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