- A100 support via mma.16816 - Thread swizzling for conflict-free shared memory accesses without padding - Complete overhaul of the LLVM code generation in codegen/selection/generator.cc to remove overengineering - Added debugging capabilities in the Python binding - Compilation error for kernels that spill
149 lines
4.6 KiB
C++
149 lines
4.6 KiB
C++
#include "triton/codegen/analysis/axes.h"
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#include "triton/ir/utils.h"
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#include "triton/ir/instructions.h"
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#include "triton/ir/type.h"
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#include <iostream>
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namespace triton{
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namespace codegen{
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namespace analysis{
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axes::axes() {}
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void axes::update_graph_reduce(ir::instruction *i) {
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auto* red = static_cast<ir::reduce_inst*>(i);
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unsigned axis = red->get_axis();
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ir::value *arg = red->get_operand(0);
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auto in_shapes = arg->get_type()->get_tile_shapes();
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unsigned current = 0;
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for(unsigned d = 0; d < in_shapes.size(); d++){
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if(d == axis)
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continue;
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graph_.add_edge({i, current++}, {arg, d});
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}
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}
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void axes::update_graph_reshape(ir::instruction *i) {
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auto* reshape = static_cast<ir::reshape_inst*>(i);
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// operands
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ir::value *op = reshape->get_operand(0);
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// shapes
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auto op_shapes = op->get_type()->get_tile_shapes();
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auto res_shapes = reshape->get_type()->get_tile_shapes();
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// construct edges
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unsigned current = 0;
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bool is_skewed = false;
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for(unsigned d = 0; d < res_shapes.size(); d ++){
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bool same_shape = res_shapes[d] == op_shapes[current];
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// either add edge between axis or just add a node in the graph
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if(!is_skewed && same_shape)
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graph_.add_edge({i, d}, {op, current++});
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else
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graph_.add_edge({i, d}, {i, d});
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// reshaping is skewed
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if(res_shapes[d] > 1 && !same_shape)
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is_skewed = true;
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}
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}
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void axes::update_graph_trans(ir::instruction *i) {
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auto *trans = static_cast<ir::trans_inst*>(i);
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ir::value *op = trans->get_operand(0);
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auto perm = trans->get_perm();
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// add edge between axis perm[d] and axis d
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for(unsigned d = 0; d < perm.size(); d++)
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graph_.add_edge({i, perm[d]}, {op, d});
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}
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void axes::update_graph_broadcast(ir::instruction *i) {
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auto *broadcast = static_cast<ir::broadcast_inst*>(i);
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auto shapes = broadcast->get_type()->get_tile_shapes();
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ir::value *op = broadcast->get_operand(0);
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ir::type *op_ty = op->get_type();
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const auto& op_shapes = op_ty->get_tile_shapes();
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// add edge between non-broadcast axes
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for(unsigned d = 0; d < shapes.size(); d ++)
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if(op_shapes[d] == shapes[d])
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graph_.add_edge({i, d}, {op, d});
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}
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void axes::update_graph_dot(ir::instruction *i) {
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auto *dot = static_cast<ir::dot_inst*>(i);
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auto shapes = dot->get_type()->get_tile_shapes();
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ir::value *A = dot->get_operand(0);
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ir::value *B = dot->get_operand(1);
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ir::value *D = dot->get_operand(2);
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// add edges between result and accumulator
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for(unsigned d = 0; d < shapes.size(); d++)
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graph_.add_edge({dot, d}, {D, d});
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}
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void axes::update_graph_elementwise(ir::instruction *i, bool connect_ret) {
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if(i->get_num_operands() == 0)
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return;
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ir::value *op = i->get_operand(0);
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if(!op->get_type()->is_tile_ty())
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return;
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auto rank = op->get_type()->get_tile_rank();
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for(unsigned d = 0; d < rank; d++)
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for(ir::value* opx: i->ops())
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for(ir::value* opy: i->ops()){
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if(connect_ret && !i->get_type()->is_void_ty())
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graph_.add_edge({i, d}, {opx, d});
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graph_.add_edge({opx, d}, {opy, d});
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}
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}
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void axes::update_graph_no_edge(ir::instruction *i) {
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if(!i->get_type()->is_tile_ty())
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return;
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auto rank = i->get_type()->get_tile_rank();
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for(unsigned d = 0; d < rank; d++)
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graph_.add_edge({i, d}, {i, d});
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}
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void axes::update_graph(ir::instruction *i) {
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switch (i->get_id()) {
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case ir::INST_REDUCE: return update_graph_reduce(i);
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case ir::INST_RESHAPE: return update_graph_reshape(i);
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case ir::INST_SPLAT: return update_graph_no_edge(i);;
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case ir::INST_TRANS: return update_graph_trans(i);
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case ir::INST_BROADCAST: return update_graph_broadcast(i);
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case ir::INST_DOT: return update_graph_dot(i);
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case ir::INST_COPY_TO_SHARED: return update_graph_no_edge(i);
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case ir::INST_MASKED_LOAD_ASYNC:return update_graph_elementwise(i, false);
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case ir::INST_COPY_FROM_SHARED: return update_graph_no_edge(i);
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case ir::INST_RECOALESCE: return update_graph_no_edge(i);
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default: return update_graph_elementwise(i);
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}
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return;
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}
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int axes::get(ir::value *value, unsigned dim) {
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return axes_.at({value, dim});
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}
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std::vector<int> axes::get(ir::value *value) {
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std::vector<int> result;
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for(size_t d = 0; d < value->get_type()->get_tile_rank(); d++)
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result.push_back(this->get(value, d));
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return result;
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}
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void axes::run(ir::module &mod) {
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// make graph
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graph_.clear();
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ir::for_each_instruction(mod, [this](ir::instruction *x) {
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update_graph(x);
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});
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// find connected components
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graph_.connected_components(nullptr, &axes_);
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}
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}
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}
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}
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