153aecb339
`insert_slice_async` is decomposed into `load + insert_slice` in the backend. Not sure if V100 perf can match the master branch though in this way. Maybe the performance can be improved if instructions are arranged in the following form: ``` %0 = load %1 = load %2 = load ... insert_slice %0 insert_slice %1 insert_slice %2 ``` Tested on A100 when manually enabling this decomposition. Tests on V100 haven't been integrated yet, we can divide the tests into two phases: 1. Test only load, insert_slice, and insert_slice_async, given TritonGPU IRs in `test_backend.py`. 2. End to end gemm tests on V100.
45 lines
1.4 KiB
C++
45 lines
1.4 KiB
C++
#include "triton/Analysis/Utility.h"
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#include "mlir/IR/Dialect.h"
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#include "triton/Dialect/Triton/IR/Dialect.h"
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#include "triton/Dialect/TritonGPU/IR/Dialect.h"
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namespace mlir {
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bool isSharedEncoding(Value value) {
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auto type = value.getType();
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if (auto tensorType = type.dyn_cast<RankedTensorType>()) {
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auto encoding = tensorType.getEncoding();
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return encoding && encoding.isa<triton::gpu::SharedEncodingAttr>();
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}
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return false;
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}
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bool maybeSharedAllocationOp(Operation *op) {
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// TODO(Keren): This function can be replaced by adding
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// MemoryEffectOpInterface. We can then use the MemoryEffectOpInterface to
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// query the memory effects of the op.
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auto *dialect = op->getDialect();
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return dialect &&
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(dialect->getTypeID() ==
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mlir::TypeID::get<triton::gpu::TritonGPUDialect>() ||
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dialect->getTypeID() == mlir::TypeID::get<triton::TritonDialect>() ||
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dialect->getTypeID() ==
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mlir::TypeID::get<arith::ArithmeticDialect>() ||
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dialect->getTypeID() == mlir::TypeID::get<tensor::TensorDialect>());
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}
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bool maybeAliasOp(Operation *op) {
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return isa<tensor::ExtractSliceOp>(op) ||
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isa<triton::gpu::InsertSliceAsyncOp>(op) ||
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isa<tensor::InsertSliceOp>(op);
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}
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std::string getValueOperandName(Value value, AsmState &state) {
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std::string opName;
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llvm::raw_string_ostream ss(opName);
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value.printAsOperand(ss, state);
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return opName;
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}
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} // namespace mlir
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