3413aad582
- Added alloc const - Added atomics - Pruning tuning space - Added example for dot/conv/shift - Bugfixes
94 lines
2.7 KiB
Plaintext
94 lines
2.7 KiB
Plaintext
//
|
|
// Generated by NVIDIA NVVM Compiler
|
|
//
|
|
// Compiler Build ID: CL-24817639
|
|
// Cuda compilation tools, release 10.0, V10.0.130
|
|
// Based on LLVM 3.4svn
|
|
//
|
|
|
|
.version 6.3
|
|
.target sm_60
|
|
.address_size 64
|
|
|
|
// .globl _Z25shift_cuda_forward_kernelPKfPKiPfiiii
|
|
|
|
.visible .entry shift(
|
|
.param .u64 _Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_0,
|
|
.param .u64 _Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_1,
|
|
.param .u64 _Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_2,
|
|
.param .u32 _Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_3,
|
|
.param .u32 _Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_4,
|
|
.param .u32 _Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_5,
|
|
.param .u32 _Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_6
|
|
)
|
|
{
|
|
.reg .pred %p<10>;
|
|
.reg .f32 %f<2>;
|
|
.reg .b32 %r<31>;
|
|
.reg .b64 %rd<13>;
|
|
|
|
|
|
ld.param.u64 %rd1, [_Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_0];
|
|
ld.param.u64 %rd3, [_Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_1];
|
|
ld.param.u64 %rd2, [_Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_2];
|
|
ld.param.u32 %r3, [_Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_3];
|
|
ld.param.u32 %r4, [_Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_4];
|
|
ld.param.u32 %r5, [_Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_5];
|
|
ld.param.u32 %r6, [_Z25shift_cuda_forward_kernelPKfPKiPfiiii_param_6];
|
|
cvta.to.global.u64 %rd4, %rd3;
|
|
mov.u32 %r7, %ntid.x;
|
|
mov.u32 %r8, %ctaid.x;
|
|
mov.u32 %r9, %tid.x;
|
|
mad.lo.s32 %r1, %r7, %r8, %r9;
|
|
mul.lo.s32 %r10, %r4, %r3;
|
|
mul.lo.s32 %r11, %r10, %r5;
|
|
mul.lo.s32 %r12, %r11, %r6;
|
|
mul.lo.s32 %r13, %r5, %r4;
|
|
mul.lo.s32 %r14, %r13, %r6;
|
|
rem.s32 %r15, %r1, %r14;
|
|
sub.s32 %r16, %r1, %r15;
|
|
mul.lo.s32 %r17, %r6, %r5;
|
|
div.s32 %r18, %r15, %r17;
|
|
mul.lo.s32 %r19, %r18, %r17;
|
|
sub.s32 %r20, %r15, %r19;
|
|
div.s32 %r21, %r20, %r5;
|
|
mul.lo.s32 %r22, %r21, %r6;
|
|
sub.s32 %r23, %r20, %r22;
|
|
shl.b32 %r24, %r18, 1;
|
|
mul.wide.s32 %rd5, %r24, 4;
|
|
add.s64 %rd6, %rd4, %rd5;
|
|
ld.global.nc.u32 %r25, [%rd6];
|
|
add.s32 %r26, %r25, %r21;
|
|
ld.global.nc.u32 %r27, [%rd6+4];
|
|
add.s32 %r28, %r23, %r27;
|
|
add.s32 %r29, %r16, %r19;
|
|
mad.lo.s32 %r30, %r26, %r5, %r29;
|
|
add.s32 %r2, %r30, %r28;
|
|
setp.lt.s32 %p1, %r1, %r12;
|
|
setp.gt.s32 %p2, %r26, -1;
|
|
and.pred %p3, %p1, %p2;
|
|
setp.lt.s32 %p4, %r26, %r5;
|
|
and.pred %p5, %p3, %p4;
|
|
setp.gt.s32 %p6, %r28, -1;
|
|
and.pred %p7, %p5, %p6;
|
|
setp.lt.s32 %p8, %r28, %r6;
|
|
and.pred %p9, %p7, %p8;
|
|
@!%p9 bra BB0_2;
|
|
bra.uni BB0_1;
|
|
|
|
BB0_1:
|
|
cvta.to.global.u64 %rd7, %rd1;
|
|
mul.wide.s32 %rd8, %r1, 4;
|
|
add.s64 %rd9, %rd7, %rd8;
|
|
ld.global.nc.f32 %f1, [%rd9];
|
|
cvta.to.global.u64 %rd10, %rd2;
|
|
mul.wide.s32 %rd11, %r2, 4;
|
|
add.s64 %rd12, %rd10, %rd11;
|
|
st.global.f32 [%rd12], %f1;
|
|
|
|
BB0_2:
|
|
ret;
|
|
}
|
|
|
|
|