153aecb339
`insert_slice_async` is decomposed into `load + insert_slice` in the backend. Not sure if V100 perf can match the master branch though in this way. Maybe the performance can be improved if instructions are arranged in the following form: ``` %0 = load %1 = load %2 = load ... insert_slice %0 insert_slice %1 insert_slice %2 ``` Tested on A100 when manually enabling this decomposition. Tests on V100 haven't been integrated yet, we can divide the tests into two phases: 1. Test only load, insert_slice, and insert_slice_async, given TritonGPU IRs in `test_backend.py`. 2. End to end gemm tests on V100.
41 lines
1.1 KiB
C++
41 lines
1.1 KiB
C++
#ifndef TRITON_TARGET_LLVMIRTRANSLATION_H
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#define TRITON_TARGET_LLVMIRTRANSLATION_H
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#include "llvm/ADT/StringRef.h"
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#include <memory>
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#include <string>
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#include <vector>
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namespace llvm {
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class Module;
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class LLVMContext;
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} // namespace llvm
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namespace mlir {
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class ModuleOp;
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} // namespace mlir
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namespace mlir {
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namespace triton {
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// add external dependent libs
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void addExternalLibs(mlir::ModuleOp &module,
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const std::vector<std::string> &names,
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const std::vector<std::string> &paths);
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// Translate TritonGPU dialect to LLVMIR, return null if failed.
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std::unique_ptr<llvm::Module>
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translateTritonGPUToLLVMIR(llvm::LLVMContext *llvmContext,
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mlir::ModuleOp module,
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int computeCapability);
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// Translate mlir LLVM dialect to LLVMIR, return null if failed.
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std::unique_ptr<llvm::Module>
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translateLLVMToLLVMIR(llvm::LLVMContext *llvmContext, mlir::ModuleOp module);
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bool linkExternLib(llvm::Module &module, llvm::StringRef path);
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} // namespace triton
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} // namespace mlir
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#endif // TRITON_TARGET_LLVMIRTRANSLATION_H
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