d8d6b715c8
Improved codegen for the Ampere GPUs.
* Make the layout pass recognize the multistage pipelined pattern.
* Now the pipeline pass can automate the multistage pipelining transformation.
* Remove extra barriers (from the prefetch pass & WAR) on Ampere.
* Update the code generator (generator.cc) to make Triton generate n-buffered shared memory loads/stores.
73 lines
1.6 KiB
C++
73 lines
1.6 KiB
C++
#ifndef TDL_INCLUDE_CODEGEN_BARRIERS_H
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#define TDL_INCLUDE_CODEGEN_BARRIERS_H
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#include <vector>
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#include <map>
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#include <list>
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#include <set>
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#include "triton/codegen/target.h"
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namespace triton {
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namespace ir {
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class module;
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class basic_block;
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class instruction;
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class masked_load_async_inst;
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class value;
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class builder;
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}
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namespace codegen{
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namespace analysis{
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class allocation;
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class liveness;
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class layouts;
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class cts;
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class shared_layout;
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}
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namespace transform{
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class prefetch;
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class membar {
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private:
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typedef std::pair<unsigned, unsigned> interval_t;
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typedef std::set<ir::value*> val_set_t;
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typedef std::vector<ir::value*> val_vec_t;
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private:
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bool intersect(const val_set_t &X, const val_set_t &Y);
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bool check_safe_war(ir::instruction* i);
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int group_of(triton::ir::value *i, std::vector<triton::ir::value *> &async_write);
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bool intersect_with(analysis::shared_layout* a_layout, analysis::shared_layout* b_layout);
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val_set_t intersect_with(const val_set_t& as, const val_set_t& bs);
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void transfer(ir::basic_block *block, val_vec_t &async_write, val_set_t &sync_write, val_set_t &sync_read,
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std::set<triton::ir::value *> &safe_war, bool &inserted, ir::builder &builder);
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public:
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membar(analysis::liveness *liveness, analysis::layouts *layouts, analysis::allocation *alloc,
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transform::prefetch *prefetch, target* tgt):
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liveness_(liveness), layouts_(layouts), alloc_(alloc), prefetch_(prefetch), tgt_(tgt) {}
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void run(ir::module &mod);
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private:
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analysis::liveness *liveness_;
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analysis::layouts *layouts_;
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analysis::allocation *alloc_;
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transform::prefetch *prefetch_;
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target* tgt_;
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};
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}
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}
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}
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#endif
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