[codegen/selection] bugfix in code generation for reduction instructions
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@@ -787,8 +787,8 @@ void selection::lower_tile_instruction(ir::instruction *ins, llvm::IRBuilder<> &
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// reduce within warp
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Value *shfl = Intrinsic::getDeclaration(builder.GetInsertBlock()->getModule(), Intrinsic::nvvm_shfl_sync_bfly_f32);
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for (int i = 16; i > 0; i >>= 1){
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Value *rhs = builder.CreateCall(shfl, {builder.getInt32(0x1f), partial,
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builder.getInt32(i), builder.getInt32(0xffffffff)});
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Value *rhs = builder.CreateCall(shfl, {builder.getInt32(0xffffffff), partial,
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builder.getInt32(i), builder.getInt32(0x1f)});
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partial = builder.CreateFAdd(partial, rhs);
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}
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// reduce within block
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@@ -58,7 +58,7 @@ void batchnorm(fp32 *Y, fp32 *M, fp32 *V,
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restrict read_only fp32 *G,
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restrict read_only fp32 *B,
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int32 DHWN) {
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int32 rx[TM] = get_global_range[TM](0);
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int32 rx[TM] = 0 ... TM;
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fp32 *px[TM];
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fp32 x[TM];
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int32 c = get_range_id(0);
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@@ -82,6 +82,7 @@ void batchnorm(fp32 *Y, fp32 *M, fp32 *V,
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x = *px;
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x = x - mean;
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var = var + x*x;
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px = px + TM;
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}
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fp32 v = __sum(var);
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fp32 *pv = V + c;
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